FPGA/SoC/Verilog/HLS

This open-source site is designed to support the educational needs of students, engineers, and enthusiasts in the fields of FPGA/ASIC, SoC, and HLS. The content and lab exercises available here draw upon materials from several reputable sources with modifications, including workshops offered by AMD/Xilinx link, the “Parallel Programming for FPGAs” course link at UCSD, “Digital Computer Design” course link at Clemson, and the “Parallel Programming on FPGAs” course link at Georgia Tech. Educators are encouraged to incorporate these resources into their curriculum.

Contents:

• Preparation

• Verilog Labs

• FPGA/SoC Labs

• HLS Labs

Acknowledgement

• This effort is partially supported by Cadence Design Systems through Clemson Cadence Project link.
• This effort is partially supported by NSF grants CNS-2027069, CCF-2106750, and CNS-2438325, as well as ONR grant N000142412623.
• Many Ugrad and Grad students from Clemson University and the University of Rhode Island (URI) contributed to this repo.
• Facutly members: Prof. Qing (Ken) Yang link from URI and Prof. Tao Wei link from Clemson.